1. Field of the Invention
This invention generally relates to a simulation method and apparatus, and, in particular, to a method and system for converting a simulation program written by a function description language into a compiled simulation program which is suitable for use in verifying the operation, function, logic of a circuit, such as a semiconductor integrated circuit and an electronics circuit, and a system in the field of CAD (computer Aided Design).
2. Description of the Prior Art
Because of the recent technological advancement in the ASIC technology, it is now possible to design an integrated circuit having 1 million gates. It is virtually impossible to design such a high density IC manually and the recent trend is to use the so-called top-down design technique. Ideally speaking, in designing an IC based on the top-down scheme, a programming language is used at the initial stage and the subsequent steps are carried out automatically. However, in reality, not all of the subsequent steps are automated and the typical current top-down design proceeds as follows.
1. Determination of specification PA0 2. System design PA0 3. Function design PA0 4. Logic design PA0 5. Layout design
In designing the function at step 3 above, use is made of the function description language, and using this as an input, a function simulation is carried out to verify the functionality of the designed function. The function description language is the language designed to describe the specification of a circuit to be designed. The use of such a function description language is advantageous because designing can be carried out without relying on a particular technology and in addition designing can be carried out commensurate with the manner of thinking of a human being. The function description language is a high level language like a programming language, such as the C language, so that a function can be described without determining an actual circuit.
The currently most commonly used function description languages are VHDL (IEEE standard, system 1076) and Verilog-HDL. The Verilog-HDL is currently more used and a simulator called Verilog-XL is also available for effecting simulation using the Verilog-HDL language.
In the Verilog-HDL, all of the functions are defined in a modular form, and each module is defined between a pair of reserved words "module" and "endmodule." as shown in FIG. 1. A plurality of modules may be provided in sequence and the modules may be arranged in a hierarchical structure. Each module has an input and an output, through which data can be exchanged with another module. Each module may have three kinds of in-module descriptions, i.e., (1) declaration of variables (input, output, reg, integer, etc.), (2) instance definition and (3) behavior description. When a module is nested in another module, the nested module is called an instance.
There are four kinds of the in-module behavior description and they are (1) "initial", (2) "always", (3) "task" and (4) "function" blocks. The "initial" block is an execution unit which is executed only once upon initiation of simulation. The "always" block is an execution unit which is repeatedly executed upon initiation of simulation. The "task" block is an execution unit which is called by the "initial" and "always" blocks. The "function" block is a function unit which is called by the "initial" and "always" blocks. A specific module modeling an ADDER described using the Verilog-HDL is illustrated in FIG. 2 as an example.
The main feature of Verilog-HDL resides in its ability to carry out a parallel processing operation. The in-module "initial" and "always" blocks constitute parallel processing units. In order to support the parallel processing of each of the modules, use is made of two parallel process control functions, i.e., (1) event control function and (2) delay control function. A statement starting with symbol "@" defines an event control function, and its function is to halt the processing of a block under execution until a trigger activated by another parallel block has arrived. On the other hand, a statement starting with symbol "#" defines a delay control function, and its function is to halt the execution of its block over a designated period of time.
Since such parallel processing control functions are provided, a number of modules can be executed properly without any interference. However, a program written by the Verilog-HDL can be executed only in an interpreter mode as it is, such as the BASIC language, so that it takes an exorbitant amount of time for execution. As the circuit to be designed becomes more complicated, the execution time increases significantly beyond a tolerable limit. A similar situation exists in the remaining function description language, so that there has been a need to devise a method and apparatus for increasing the speed of execution of a program written by the function description language.